SIMDE™ V2.1 Release 201006

- Signal Integrity Model Development Environment

- Introduction slides

- Datasheet

SIMDE™ Overview

Simulation is more and more important for High-Speed system design. It can help you optimize your design performance, reduce your design cycle, lower your prototype cost and accelerate your design to market. Electrical I/O modeling is the starting point for your advanced chip and system simulations. It enables faster and more accurate simulations.
Signal Integrity Model Development Environment (SIMDE™) provides a graphical model development and validation environment. It gives direct method for model development and validation. It focuses on automated SI model generation and validation processes (IBIS and SPICE macromodeling in this version and Verilog-A / VHDL-AMS in the future).

Create more accurate models, more quickly.

Integrated with HSpice, Spectre, Eldo and TISpice3

IBIS Model Generation and Validation

SIMDE™ provides an automate IBIS buffer model generation and validation process. It includes a graphical interface for mapping the SPICE buffer nodes as well as using the schematic type editing mode for other nodes settings. It automatically runs Synopsys HSpice to extract the buffer's behavior from the Spice buffer. There is no need for manual editing during the process.

SIMDE™ has a seamless validation process for IBIS buffer model generation. It remembers all the settings for the Spice model when generating the IBIS buffer and uses them for your IBIS model validation on your own topologies. It also provides a detailed DPI (Differential Peak Index) and DAI (Differential Average Index), and reports any differences between the Spice and IBIS buffer simulations as well as the visual waveform inspection.

SIMDE™ contains:

• Automatic Spice buffer node mapping capability
• Graphical node setting capability
• Automatic Spice to IBIS buffer extraction process
• Auto Die-Capacitance extraction option for both driving and receiving mode.
• Capable for All IBIS Input / Output / IO model types and differential buffers (Pseudo, half and true differential pair) extractions
• Easy setup for Typical / Minimum / Maximum corner extractions
• Build-in IBIS standard buffer test fixtures
• Supports HSpice, Spectre, Eldo and TISpice3 integrations
• Extraction using existing data for IBIS and IBIS differential models
• IBIS buffer model validation sheet with freedom of topology settings
• Detail validation reports with Differential Peak Index (DPI) and Differential Average Index (DAI)
• IBIS buffer curves visual inspection and report for On-die termination, non-monotonic and load-line crossing verification. (SignalMeth™ IBIS Application Module)
• Ease-of-use IBIS File generation wizard with Model Selector Builder

Spice Macromodel Generation, Fitting and Validation

SIMDE™ also provides an integrated flow for Spice Macromodel Generation, Fitting and Validation. It allows a user to start from scratch or start from the base elements, using our integrated standard library elements or elements you made as black-boxes. Its hierarchy structure will give the user a clean graphical structural view from the different levels.
The Fitting process allows the user to load the Golden waveform for the macromodel optimization process. It can swing many parameters and find the best settings for the case that fits the Golden source the best.
The validation process take place in an easy to use environment for verifying the macromodel that you just built for a specific load validation. You may also import 3rd party models for validation.
The Spice macromodel is powerful and fast. It can virtually model everything you may need.

Macromodeling, the alternative, advanced method for IP protected, high performance device modeling.